1. Field of the Invention
This invention relates to the field of DC voltage generators and in particular to an on-chip DC voltage generator.
2. Background Art
The operation of integrated circuits often requires that a signal be compared to a reference level such as a reference voltage. An external DC voltage generator is traditionally used to provide this reference signal. Using an external DC voltage generator, as will be further explained below, is disadvantageous in terms of the physical limitations of the IC and the complexity it adds to the system.
The generator is typically either a voltage divider or resistor network. Decoupling capacitors are often used to bypass the frequency-dependent noise and prevent the noise from injecting into the chip. This reference signal, Vref, is usually set at the center of the data eye pattern. A data eye pattern is the superposition of the ones and zeroes output from a high speed system or circuit. This pattern is obtained by sampling a long pseudo-random-bit-sequence output from the system under study. The horizontal width of the lines gives the jitter (phase noise) and the rise and fall times of the data pulses can be measured from the crossings of the sampled signals.
A prior art voltage generator configuration is illustrated in FIG. 1. FIG. 1 comprises a chip 100 connected to M external voltage generators 105. Each external voltage generator 105 is associated to a bank of N data lines 110 through N comparators 115. Each voltage generator 105 is connected to common ground 120. In operation each voltage generator 105 supplies a reference voltage to each comparator 115 in its associated bank. The reference voltages may differ as between each generator 105.
A comparator is an operational amplifier, or op-amp. A comparator comprises two input terminals, positive (+) and negative (xe2x88x92). The signal generated by a comparator indicates which of these two voltages is greater:
Vo=A(Vpxe2x88x92Vn)
where A is the open-loop voltage gain of the amplifier, Vp is the positive input voltage and Vn is the negative input voltage. Both Vp and Vn are node voltages with respect to ground.
There are numerous drawbacks inherent in the use of an external reference voltage source. In coupling the source to the chip, the leads necessarily occupy package pin counts and IO pads on the chip. This configuration generates noise coupling from the board, as well as noise generated by inductive Vref pins. The use of multiple components complicates board routing. Finally, external reference voltage generators require R/C components.
An on-chip DC voltage generator providing a marginable reference voltage signal is described herein. Embodiments of the present invention are Complementary Metal Oxide Semiconductor (CMOS)-based integrated circuits that generate marginable reference voltage level. One embodiment of the present invention generates a process insensitive reference voltage signal. A separate embodiment of the present invention generates a ground-bounce-noise free reference voltage signal. Another embodiment of the present invention implements a voltage margining scheme. A marginable DC voltage generator may produce several discrete Vref levels. This circuit is said to be marginable because the several voltage levels are available for use at any time.